In the process of circuit design the designer first defines the design by describing it in a formal hardware description language. Such definition takes the form of a data file.
One of the subsequent phases on the road to physical realization of the design is logic verification. In the logic verification phase the logic designer tests the design to determine if the logic design meets the specifications/requirements. One method of logic verification is simulation.
During the process of simulation a software program or a hardware engine (the simulator) is employed to imitate the running of the circuit design. During simulation the designer can get snapshots of the dynamic state of the design under test. The simulator will imitate the running of the design significantly slower than the final realization of the design. This is especially true for a software simulator where the speed could be a prohibitive factor.
In the past, to achieve close to real time simulation speeds special purpose hardware accelerated simulation engines have been developed. Such engines consist of a computer, an attached hardware unit, a compiler, and a runtime facilitator program.
Hardware accelerated simulation engine vendors have developed two main types of simulation engines comprising: Field Programmable Gate Array (FPGA) based simulation engines and ASIC based simulation engines.
A Field Programmable Gate Array (FPGA) based simulation engine employs a field of FPGA chips placed on multiple boards, connected by a network of IO lines. Each FPGA chip is preprogrammed to simulate a particular segment of the design. While these engines are achieving close to real-time speeds their capacity is limited by the size of the FPGA.
ASIC based simulation engines employ a field of ASIC chips placed on one or more boards. Such ASIC chips include two major components: the Logic Evaluation Unit (LEU) and the Instruction Memory (IM). The LEU acts as an FPGA based simulation engine that is programmed using instructions stored in the IM. The simulation of a single time step of the design is achieved in multiple simulator steps. In each of these simulation steps an instruction row is read from the IM and is used to reconfigure the LEU. The simulation step is concluded by allowing each such configured LEU to take a single step and to evaluate the design piece it represents.
ASIC based simulation engines need to perform multiple steps to simulate a single design time step. Hence they are inherently slower than FPGA based engines, although the gap is shrinking. In exchange, the capacity of ASIC based simulation engines is bigger.
The LEU has two major functions: to simulate the design piece for which it is programmed and to route various signals of the DEUT to other LEU units on the simulator engine. The latter task is achieved by employing, among other hardware elements, programmable cross-point switches.
A programmable cross-point switch is a hardware element that includes an array of input signals, an array of output signals, and an array of command signals. Assuming a fixed set of values on the command signals, the programmable cross-point switch behaves as if the output signals were directly connected to the input signals using some permutation. A different set of values on the command signals results in a different permutation
A typical implementation of a programmable cross-point switch typically employs multiple multiplexers. Each output has a private multiplexer that connects it with one of the inputs based on the values of the command signals of the multiplexer.
The capacity of an ASIC based hardware accelerated simulation engine is determined by the number of ASIC chips it employs, by the size of the IM, by the size of an instruction row, and by the size of the design piece the LEU can simulate in a single simulator step. Many of these factors are bound by technology constraints.
Clearly, a need exists to increase capacity of an ASIC based hardware accelerated simulation engine.